The present invention is relating to a semiconductor package, more particularly to a semiconductor build-up package with expanded electrical function.
In the semiconductor packaging industry, chips are trending to small size, high density and have a large number of terminals (the number of I/O is more than one hundred). So that there are packaging techniques of CSP (chip scale package) and FC (flip chip) package provided to encapsulate chip(s) to become a semiconductor package. Due to the intervals between adjacent contacts of chip become very small, it is difficult to plant the solder balls and then the problems of surface mounting fail become more serious. So that reliability of electrical function and yield of semiconductor package would decrease largely, and the technology of CSP (chip scale package) or FC (flip chip) package is not suitable to be worked out.
In order to solve the problems mentioned above, a semiconductor package is brought up from U.S. Pat. No. 6,271,469 xe2x80x9cdirect build-up layer on an encapsulated die packagexe2x80x9d. As shown in FIG. 1, the semiconductor build-up package 100 comprises a die 102, an encapsulating material 112, a first dielectric layer 118 and a second dielectric layer 126. The die 102 has an active surface 106 forming a plurality of contacts 108. The encapsulating material 112 covers the inactive surface 114 and sides 116 of the die 102 for protecting the die 102. The encapsulating material 112 has a surface that is coplanar to the active surface 106 of the die 102 for providing a substantially planar area for building up dielectric layers 118 and 126. The first dielectric layer 118, made of dielectric materials such as silicon oxide or silicon nitrogen, is formed on the area defined by the active surface 106 of the die 102 and the surface of the encapsulating material 112. The first dielectric layer 118 has a plurality of conductive traces 124 that are conductive metals such as copper, aluminum, or alloys thereof. The second dielectric layer 126 is formed above the first dielectric layer 118 and conductive traces 124, and has a plurality of conductive columns 132. The conductive pads 134 are formed on the second dielectric layer 126. A conductive path is constituted by one of conductive traces 124 and the corresponding conductive column 132 for electrically connecting the contacts 108 of the die 102 with the corresponding conductive pads 134. A solder mask 136 is formed on the second dielectric layer 126. Conductive pads 134 are exposed from the solder mask 136 for planting solder balls 138. Therefore, the contacts 108 of the die 102 can electrically fan out to the conductive pads 134 through the first dielectric layer 118 and the second dielectric layer 126 or more, so that it is easy for planting the solder balls 138 and surface mounting to PCB (print circuit board), etc. However in the conventional structure mentioned-above, the encapsulating material 112 is made of resin and becomes build-up forming surface of the first dielectric layer 118 and the second dielectric layer 126 without extra electrical function so that the semiconductor build-up package 100 is provided for packaging single chip.
The main object of the present invention is to provide a semiconductor build-up package that comprises a die, a circuit board and at least a dielectric layer. The circuit board carries the die and has a surface for building up a plurality of dielectric layers in order to enhance the electrical function of the semiconductor build-up package.
The secondary object of the present invention is to provide a semiconductor build-up package on which the electrical connections between the circuit board and the die are through electrical paths of the dielectric layers. Resistances, condensers and fuses are embedded in wires inside the circuit board for expanding the electrical function of the die and shortening conductive paths of connecting traces.
According to the present invention, a semiconductor build-up package comprises a die, a circuit board and at least a dielectric layer. The die has an active surface with bonding pads and an inactive surface. The circuit board has a first surface and a second surface. A cavity or a through hole is formed on the first surface for accommodating the die and there are conductive traces inside the first surface for expanding the electrical function of the build-up package. It is preferable that the circuit board is a multi-layer printed circuit board and the first surface of the circuit board is coplanar to the active surface of the die for providing an enough planar area that is necessary to build up a plurality of dielectric layers. The dielectric layers are formed in turn on the area formed by the active surface of the die and the surface of the circuit board. A plurality of conductive pads are formed on the outermost dielectric layer. The dielectric layers have at least a conductive column electrically connecting the conductive traces of the circuit board. The conductive traces and conductive columns in each dielectric layer are made of copper, aluminum or alloys thereof for providing electrical connection. Further, a plurality of solder balls, bumps or pins are formed on the conductive pads for surface mounting the semiconductor build-up package to a printed circuit board, etc. Besides, further at least a second die is mounted on the second surface of the circuit board. The second die electrically connects with the conductive traces by wire bonding or flip chip mounting technique for electrically connecting with the corresponding conductive pads through the conductive columns of the dielectric layers, so that a semiconductor build-up package with multi-chip configuration is formed. By means of the conductive traces of circuit board and the conductive columns of dielectric layers, the plurality of dies electrically fan out to the outermost conductive pads. Furthermore, the contacts of the die may electrically be connected with the conductive traces of the circuit board through the conductive columns of dielectric layers. Resistances, condensers and fuses are embedded in wires inside the circuit board for expanding the electrical function of the build-up package and shortening the conductive paths of connecting traces.